Julian Brandner

High-Performance Computing (HPC) is an important component of Europe's capacity for innovation and it is also seen as a building block of the digitization of the European industry. Reconfigurable technologies such as Field Programmable Gate Array (FPGA) modules are gaining in importance due to their energy efficiency, performance, and flexibility.
There is also a trend towards heterogeneous systems with accelerators utilizing FPGAs. The great flexibility of FPGAs allows for a large class of HPC applications to be realized with FPGAs. However, FPGA programming has mainly been reserved for specialists as it is very time consuming. For that reason, the use of FPGAs in areas of scientific HPC is still rare today.
In the HPC environment, there are various programming models for heterogeneous systems offering certain types of accelerators. Common models include OpenCL (http://www.opencl.org), OpenACC (https://www.openacc.org) and OpenMP (https://www.OpenMP.org). These standards, however, are not yet available for the use with FPGAs.

Goals of the ORKA project are:

1. Development of an OpenMP 4.0 compiler targeting heterogeneous computing platforms with FPGA accelerators in order to simplify the usage of such systems.
2. Design and implementation of a source-to-source framework transforming C/C++ code with OpenMP 4.0 directives into executable programs utilizing both the host CPU and an FPGA.
3. Utilization (and improvement) of existing algorithms mapping program code to FPGA hardware.
4. Development of new (possibly heuristic) methods to optimize programs for inherently parallel architectures.

In 2018, the following important contributions were made:

• Development of a source-to-source compiler prototype for the rewriting of OpenMP C source code (cf. goal 2).
• Development of an HLS compiler prototype capable of translating C code into hardware. This prototype later served as starting point for the work towards the goals 3 and 4.
• Development of several experimental FPGA infrastructures for the execution of accelerator cores (necessary for the goals 1 and 2).

In 2019, the following significant contributions were achieved:

• Publication of two peer-reviewed papers: "OpenMP on FPGAs - A Survey" and "OpenMP to FPGA Offloading Prototype using OpenCL SDK".
• Improvement of the source-to-source compiler in order to properly support OpenMP-target-outlining for FPGA targets (incl. smoke tests).
• Completion of the first working ORKA-HPC prototype supporting a complete OpenMP-to-FPGA flow.
• Formulation of a genome for the pragma-based genetic optimization of the high-level synthesis step during the ORKA-HPC flow.
• Extension of the TaPaSCo composer to allow for hardware synchronization primitives inside of TaPaSCo systems.

In 2020, the following significant contributions were achieved:

• Improvement of the Genetic Optimization.
• Engineering of a Docker container for reliable reproduction of results.
• Integration of software components from project partners.
• Development of a plugin architecture for Low-Level-Platforms.
• Implementation and integration of two LLP plugin components.
• Broadening of the accepted subset of OpenMP.
• Enhancement of the test suite.

In 2021, the following significant contributions were achieved:

• Enhancement of the benchmark suite.
• Enhancement of the test suite.
• Successful project completion with live demo for the project sponsor.
• Publication of the paper "ORKA-HPC - Practical OpenMP for FPGAs".
• Release of the source code and the reproduction package.
• Enhancement of the accepted OpenMP subset with new clauses to control the FPGA related transformations.
• Improvement of the Genetic Optimization.
• Comparison of the estimated performance data given by the HLS and the real performance.
• Synthesis of a linear regression model for performance prediction based on that comparison.
• Implementation of an infrastructure for the translation of OpenMP reduction clauses.
• Automated translation of the OpenMP pragma `parallel for` into a parallel FPGA system.

In 2022, the following significant contributions were achieved:

• Generation and publication of an extensive dataset on HLS area estimates and actual performance.
• Creation and comparative evaluation of different regression models to predict actual system performance from early (area) estimates.
• Evaluation of the area estimates generated by the HLS.
• Publication of the paper “Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling”.
• Development of a method to detect and remove redundant read operations in FPGA stencil codes based on the polyhedral model.
• Implementation of the method for ORKA-HPC.
• Quantitative evaluation of that method to show the strength of the method and to show when to use it.
• Publication of the paper “Employing Polyhedral Methods to Reduce Data Movement in FPGA Stencil Codes”.

In 2023, the following significant contributions were achieved:

• Development and implementation of an optimization method for canonical loop shells (e.g. from OpenMP target regions) for FPGA hardware generation using HLS. The core of the method is a loop restructuring based on the polyhedral model that uses loop tiling, pipeline processing, and port widening to avoid unnecessary data transfers from/to the onboard RAM of the FPGA, increase the number of parallel active circuits, maximize data throughput to FPGA board RAM, and hide read/write latencies.
• Quantitative evaluation of the strengths and application areas of this optimization method using ORKA-HPC.
• Publication of the method in the conference paper "Employing polyhedral methods to optimize stencils on FPGAs with stencil-specific caches, data reuse, and wide data bursts".
• Publication of a reproduction package for the optimization method.
• Presentation of the method at the conference "14th International Workshop on Polyhedral Compilation Techniques" in a half-hour talk.
• Development of a method for the fully automatic integration of multi-purpose caches into FPGA solutions generated from OpenMP.
• Evaluation of multi-purpose caches in combination with HLS generated hardware blocks.
• Publication of the paper "Multipurpose Cacheing to Accelerate OpenMP Target Regions on FPGAs" (Best Paper Award).

Since 1977 the International Collegiate Programming Contest (ICPC) takes place every year. Teams of three students try to solve about 13 programming problems within five hours. What makes this task even harder, is that there is only one computer available per team. The problems demand for solid knowledge of algorithms from all areas of computer science and mathematics, e.g., graphs, combinatorics, strings, algebra, and geometry. To solve the problems, the teams need to find a correct and efficient algorithm and implement it.The ICPC consists of three rounds. First, each participating university hosts a local contest to find the up to three teams that are afterwards competing in one of the various regional contests. Germany lies in the catchment area of the Northwestern European Regional Contest (NWERC) with competing teams from Great Britain, Benelux, Scandinavia, etc. The winners of all regionals in the world (and some second place holders) advance to the world finals in spring of the following year (2023 in Sharm El Sheikh, Egypt).

On January 27, 2024, the Winter Contest took place once again. 108 teams from 17 universities participated, including 15 teams from Erlangen. Our best team finished 32nd. On June 22, the German Collegiate Programming Contest was held at several German universities, with 15 teams from Erlangen. The best FAU team secured the 22nd position out of 94 participating teams from all over Germany. The NWERC took place on November 24 in Delft. FAU was represented by one team, which finished in the 19th position among 80 participating teams. As usual, we also conducted the main seminar “Hello World! - Advanced Programming” in 2024.